HEF4006BP-DIP

The HEF4006B is an 18-stage shift register arranged as two 4-stage and two 5-stage shift registers with a common clock input (CP)’. The two 4-stage shift registers each have a data input (DA, DB) and a data output (O3A, O3B); the two 5-stage shift registers each have a data input (DC, DD) and data outputs from the fourth and fifth stages (O3C, O4C, O3D, O4D). The registers can be operated in parallel or interconnected to form a single shift register of up to 18 bits. Data are shifted into the first register position of each register from the data inputs (DA to DD) and all the data in each register are shifted one position to the right on the HIGH to LOW transition of CP.