The 74HC138D is a high speed CMOS 3-to-8 DECODER fabricated with silicon gate C
It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power
When the device is enabled, 3 Binary Select inputs (A, B and C) determine which one of the outputs (Y0 -
will go low.
When enable input G1 is held low or either
G2B is held high, decoding function is inhibited and all
outputs go high.
G2B inputs are provided to ease cascade connection and for use as an address decoder for memory
All inputs are equipped with protection circuits against static discharge or transient excess voltage.
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